The present invention relates to a fabrication system and a fabrication method capable of fabricating various kinds of semiconductor devices for a short period of time.
In automated fabricating plants, various kinds of works are processed in a plurality of automated fabrication apparatuses. In such a fabricating plant, the scheduling of processing is determined in terms of the appointed data of works, working efficiency, and the minimized amount of semi-finished products between processing apparatuses. To smoothly perform the above processing in the automated fabricating plant, it is important to enhance the reliability of each processing apparatus and a system managing computer; and it is more important to enhance the function of managing the whole fabricating system. This is because, in the automated fabricating plant, the fabricating system is automatically operated, and it is managed by the unit having the function of managing the fabricating system.
In particular, in a fabricating plant for semiconductor devices, a plurality of semiconductor wafers of various kinds are processed using a plurality of processing apparatuses according to processing steps and processing conditions determined for every kinds of wafers. In some cases, the same apparatus is used for different processes, and thereby the repeating of the processing becomes very complicated. Accordingly, a high management function is required for the fabricating system for semiconductor devices. One example of the complicated processing in the fabricating system for semiconductor devices will be described. A circuit element used in assembly of a semiconductor device is formed of at least one semiconductor chip. In general, the chips are obtained by cutting circuit element areas arranged on a semiconductor wafer in the longitudinal and lateral directions, along the boundaries. Various processing steps are required to form circuit element areas on a semiconductor wafer. For example, processes of forming areas including the desired impurities atoms on a semiconductor wafer includes (1) a process of cleaning the wafer; (2) a heat treatment process of oxidizing the surface of the wafer; (3) a resist coating process of coating a photoresist on an oxide film and drying it; (4) an exposing process of exposing the desired area of a resist by an energy particle beam such as a light beam, electron beam or X-ray; (5) a developing process of selectively removing the exposed or non-exposed portion of the photoresist; (6) an etching process of removing the exposed oxide film using the resist partially remaining on the oxide film as a mask; (7) a resist removing process of removing the resist partially remaining on the oxide film; (8) an impurities introducing process of depositing impurities on the wafer or allowing them to permeate a surface layer portion by exposing the wafer in the impurity atmosphere using the oxide film as a mask, or using CVD, vapor-deposition or ion implantation; and diffusing the impurities up to the desired depth by heating; and (9) an etching process of removing the unnecessary oxide film or the like on the surface of the wafer. A sequence of processes from the resist removing process (3) to the developing process (5) or to a resist baking process applied after the developing process as needed are called photolithography processes, and which are repeatedly used for the formation of the circuit element. Namely, the photolithgraphy processes are used for the formation of a metal film and the formation of a passivation layer, other than the formation of the impurity introducing area. In this way, various processes are applied to the wafer, and further, some processes, for example included in the photolithography processes are repeatedly applied to the same semiconductor wafer by twice or more. In general, the number and order of various processes applied to the wafer are partially different for the kinds of products. In processing of semiconductor wafers, several hundreds of kinds of works are processed by one method selected from several tens of methods. Moreover, the number of semiconductor wafers processed simultaneously are extremely large. It is extremely difficult to process these semiconductor wafers under good management. As a result, there occur problems in that the appointed date is made longer, and the working ratio of each processing apparatus is reduced thereby lowering the number of products finished per unit time. Moreover, the cleanliness of a clean space in which semiconductor wafers are processed must be usually kept to be high. However, since many operators get around in a clean space in which processing apparatuses are disposed, dust adhering on the clothes of the operators and floors are scattered, which makes it difficult to keep the high cleanliness of the clean space. This causes a disadvantage that the dust adheres on semiconductor wafers thereby reducing the percent non-defective. To cope with this disadvantage, there has been known a method, exemplified in Japanese Patent Laid-open No. SHO 64-6540, wherein works are processed in an unmanned system for preventing the contamination of semiconductor wafers, and a sequence of processing steps are organically controlled to manage a plurality of semiconductor wafers of various kinds, thereby reducing the term of works, enhancing the percent non-defective, and lowering the number of operators.
The prior art managing system for automating the very complicated fabricating system for semiconductor devices described above has been described, for example in “Operation of LSI Production System to Reduce Development Investment and to Meet Diversified Needs” (Nikkei Microdevice, August, 1992, pp. 66-74). At the beginning of the automated fabrication, a centralized control system has been extensively performed, in which processing information in a plant is all inputted in a central computer and the work indications are performed by the computer. In this system, when the centralized control computer is normally operated, it usually grasps the whole state of the fabricating system, and thereby a high level control can be realized. However, this system is disadvantageous in that when the computer fails, the control of the fabricating system is stopped because of the absence of any means replaced with the computer. A software incorporated in the centralized control computer is of a model type including processing apparatuses and transporters, and many cases, algolizm depending on the features of processing apparatuses and transporters is incorporated therein. Accordingly, in renewal of a processing apparatus, the software incorporated in the computer must be exceedingly corrected, thus requiring a large amount of labor for the correction and expansion of the software. A distributed processing system is used to solve the above disadvantage of the centralized control system, in which the centralized computer is replaced by a plurality of computers. The management of the distributed processing system is described, for example in Japanese Patent Laid-open No. SHO 63-244730. However, even when either of the above-described managing systems is used to automate the fabricating system, the effect of shortening the term of works and the effect of increasing the number of products per unit time by enhancing the working ratio and the percent non-defective do not reach the sufficient level for achieving the suitable time/suitable amount production.
The first reason for this is that in the prior art, the transporting between a plurality of processing apparatuses is performed by a batch system, in which the so-called “lot” constituted of a plurality of semiconductor wafers is taken as a unit. The diameter of a semiconductor wafer has been enlarged for enhancing the productivity. For the purpose of performing a high accurate processing to such a semiconductor wafer, the processing in each processing apparatus has been changed from the conventional batch system to a single wafer processing. However, even in the single wafer processing apparatus, so long as semiconductor wafers are processed for each unit of lot, one processing takes a time required to process the number of semiconductor wafers constituting one lot, which makes longer the waiting time until the subsequent processing. Therefore, even if the management of products and processes is enhanced using computers, there is a limitation to the shortage of the term of works in principle. Moreover, the waiting time between specified two continued processes is greatly dependent on the lot, that is, on the semiconductor wafer, thus obstructing the improvement in percent non-defective.
The second reason for this is that, it is very difficult to optimize a plurality of complicated processes even by the control using computers in the lot processing environment, thus reducing the productivity. In a fabricating system, the number of processing apparatuses capable of performing the same process is determined on the basis of the throughput while examining the processing number for each wafer in each processing apparatus, and thus the processing ability (wafer/unit time) of each processing apparatus is equalized. However, in some cases, the fabricating system cannot actually achieve the processing ability thus calculated as a whole. Namely, it is impossible to optimize the complicated processes, the balance in the processing amount in each processing apparatus is not kept, thus reducing the productivity.
The third reason for this is that, in the fabricating system by batch transporting, a large amount of works in process (non-finished products) are required to ensure the productivity, thereby making longer the term of works. Moreover, when the term of works is made longer, the stay time of semiconductor wafers in a clean space where the fabricating system is contained is made longer, and thereby a high cleanliness of the clean space is required to prevent the reduction of percent non-defective. The fine pattern of a circuit element requires a high cleanliness, and it becomes difficult to realize a clean space with a high cleanliness, because the buildings having the clean space becomes very complicated and expensive, and a large energy is required to keep the clean space. One of the disadvantage of the prior art fabricating system by the batch transporting is to require a clean space with a high cleanliness.
To cope with the above disadvantage, in recent years, a fabricating system using a single wafer transporting has been proposed, for example in Japanese Patent Nos. HEI 4-130618 and HEI 4-199709, wherein a single wafer is transported between a plurality of processing apparatuses
The prior art fabricating system disclosed in Japanese Patent Laid-open No. HEI 4-199709 has a disadvantage in increasing the number of processing apparatuses. Even when a plurality of processes can be performed using the same processing apparatus, a plurality of processing apparatuses must be prepared in the order of the processing steps. If not so, the flows of semiconductor wafers are crossed to each other, and two or more wafers cannot be simultaneously processed in the fabricating system. As described above, for example, the photolithography processes are repeatedly used for the formation of a circuit element. The resist coating and resist baking process included in the photolithography processes is repeatedly applied to the same semiconductor wafer by twice or more. To prevent an increase in the number of processing apparatuses, the processing apparatus required in some processes must be commonly used. To commonly use the resist coating and baking process, the resist coating and resist baking apparatus must be directly connected to all of processing apparatuses for performing processes before and after the resist coating and resist baking process by means of an inter-apparatus single wafer transporter not by way of other processing apparatuses. For example, it must be connected to all of the film deposition apparatuses. It is impossible to realize such a construction by the system shown in Japanese Patent Laid-open No. HEI 4-199709.
On the contrary, in the system shown in Japanese Patent Laid-open No. HEI 4-130618, all of processing apparatuses are connected to each other by means of an inter-apparatus single wafer transporter, so that the above-described disadvantages can be solved. This is because each semiconductor wafer can be transported between any two processing apparatuses. The disadvantage of this system lies in that a plurality of semiconductor wafers are crossed to each other in processing apparatuses and transporters. Only by connecting single wafer processing apparatuses to each other by means of a single wafer transporter, it cannot be achieved to obtain a high efficiency in simultaneously processing a plurality of semiconductor wafers.
First, it is required to determine the number of processing apparatuses on the basis of the throughput while examining the processing number for each semiconductor wafer in each processing apparatus, and to equalize the processing ability (wafers/unit time) of each process. In the system shown in Japanese Patent Laid-open No. HEI 4-130618, the number of processing apparatuses is determined on the basis of a failure frequency and a repairing time, and the first processing for one wafer is completed and then the next wafer is loaded in the first processing apparatus, with a result that wafers are stayed in the processing apparatus with a lowest processing ability. To avoid the above problem, the processed amount must be reduced on the basis of the ability of the processing apparatus, which causes a disadvantage that the term of works is shortened and the wafer output is reduced. It is necessary to examine the transporter and the transporting time. In the single wafer transporting, the transporting is performed for each unit of a single wafer, so that it becomes very complicated. In the system shown in Japanese Patent Laid-open No. HEI 4-130618, the crossing of semiconductor wafers in the transporting stage is not examined. The control and management for single wafer processing and single wager transporting are also complicated, and is very difficult to be satisfactorily realized.
In the prior art systems described in Japanese Patent Laid-open Nos. HEI 4-130618 and HEI 4-199709, all of processing apparatuses are of a single wafer processing type; however, by adopting the single wafer processing for all processes, the productivity is reduced in terms of the existing throughput. The above-described prior art systems fail to examine this point, which is one reason why these systems are not extensively used.
The prior art managing system has the following problems. In either of the centralized control system and the distributed processing system, the management of the prior art fabricating system is based on a unit of the so-called lot constituted of several to 25 pieces of wafers. In this case, wafers constituting a lot are contained in a cassette case, so that the management of information for each lot can be performed by the addition of an IC card to each cassette case. The reason why such an auxiliary means is required is as follows: namely, the information to be managed in the system is large; and further, in the case that the management of information is all dependent on a computer for managing the information of the whole system, when there occurs the malfunction and system-down of the information managing computer, all of the management information in the fabricating system is lost, resulting in a large damage. In the fabricating system of the distributed processing system described in the above document “Operation of LSI Production System to Reduce Development Investment and to Meet Versified Needs” (Nikkei Microdeviec, August, 1992), an IC card is attached to each lot. A method of utilizing an identification symbol of a cassette case is disclosed, for example in Japanese Patent No. SHO 61-128512. However, as described above, a processing apparatus of the batch type has been gradually changed into that of the single wafer processing type. Moreover, the transporting between processing apparatuses has been changed from the batch type to the single wafer type. To make efficient use of the advantage of the inter-apparatus single wafer transporting which is at least partially used in the fabricating system, the management of information for each semiconductor wafer is at least partially inevitable. In the inter-apparatus transporting where wafers are transported in a manner not to be contained in a cassette case, an auxiliary storing means such as the IC card moved together with wafers having wafer information to be managed cannot be used. Moreover, since the renewing number of processing information necessary for processing in each processing apparatus becomes extremely larger than in the batch transporting, which causes a problem in that the management of information by the auxiliary storing means such as the IC card is large in the renewal frequency and is cannot be used. To cope with this problem, a method in which information on the kind and process is held in a semiconductor wafer itself is described in Japanese Patent Laid-open Nos. SHO 57-157518, SHO 58-50728, SHO 63-288009, HEI 2-292810 and HEI 5-83520. A method in which information is written in a chip is described in Japanese Patent Laid-open No. SHO 60-10641. In either method, the technique is limited only to the writing or reading of information, and it does not examine the management of information contained in a fabricating system. Since the number of the transporting between processing apparatuses becomes extremely larger, the management of information in the inter-apparatus transporter is required to be managed. In view of the foregoing, there have been required a fabricating system for semiconductor devices which is suitable for single wafer management and is capable of solving the above-described problems; and a fabricating method using the system. Moreover, there have been required a fabricating system for semiconductor devices capable of optimizing a plurality of complicated processing steps controlled by computers, improving the productivity, and reducing the term of works, in the environment of the above-described management of information of a single wafer; and a fabricating method using the system.